I am a CPU architect working at IA Core architecture group of Intel.  I got my PhD from University of Central Florida with Professor Huiyang Zhou.

Email:

Research Interests:
Computer architecture: branch prediction, instruction fetch, cache replacement, GPGPU, fault-tolerance and power efficiency.

Call for participants: the 3rd Championship Branch Prediction held with ISCA-38!

Education:

• 2003 - 2008 Ph.D., Computer Science, University of Central Florida.
• 2003 - 2005 M.S, Computer Science, University of Central Florida.
• 1997 - 2001 B.E, Computer Science and Technology, Beihang University / Beijing University of Aeronautics and Astronautics (BUAA).

Publications:

• Hongliang Gao and Chris Wilkerson, "A dueling Segmented LRU Replacement Algorithm with Adaptive Bypassing", 1st JILP Workshop on Computer Architecture Competitions (Cache Replacement Championship), held in conjunction with the 37th IEEE/ACM International Symposium on Computer Architecture (ISCA-37), June, 2010. 1st place awards of both private cache track and shared cache track. (presentation, download the code, the simulation framework).
• Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah and Shih-Lien Lu, “Trading off Cache Capacity for Low Voltage Operation”, IEEE Micro, Special Issue: Micro's Top Picks from 2008 Computer Architecture Conferences, January/February 2009.
• Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah and Shih-Lien Lu, "Trading Off Cache Capacity for Reliability to Enable Low Voltage Operation,", The 35th Annual International Symposium on Computer Architecture (ISCA-35), Beijing, China, June 2008.
• Hongliang Gao, Martin Dimitrov, Jingfei Kong, and Huiyang Zhou, “Experiencing Various Massively Parallel Architectures and Programming Models for Data-Intensive Applications”, Workshop on Computer Architecture Education (WCAE-08), held in conjunction with ISCA-35, 2008.
• Hongliang Gao, Yi Ma, Martin Dimitrov, and Huiyang Zhou, “Address-Branch Correlation: A Novel Locality for Long-Latency Hard-to-Predict Branches”, The 14th International Symposium on High Performance Computer Architecture (HPCA-14), February, 2008.
• Yi Ma, Hongliang Gao, Martin Dimitrov, and Huiyang Zhou, “Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery”, IEEE Transactions on Parallel and Distributed Systems, vol. 18, no. 8, pp. 1080-1093, August, 2007.
• Hongliang Gao and Huiyang Zhou, “PMPM: Prediction by Combining Multiple Partial Matches”, Journal of Instruction-Level Parallelism (JILP), pp. 1-18, Vol. 9, 2007.
• Hongliang Gao and Huiyang Zhou, "PMPM: Prediction by Combining Multiple Partial Matches", In the 2nd Championship Branch Prediction (CBP-2) held with the 39th International Symposium on Microarchitecture (MICRO-39), Dec. 2006. (finalist to both the realistic and idealistic tracks, code for realistic track, code for idealistic track)
• Yi Ma, Hongliang Gao, and Huiyang Zhou, "Using Indexing Functions to Reduce Conflict Aliasing in Branch Prediction Tables", IEEE Transactions on Computers (TC), August, 2006
• Hongliang Gao and Huiyang Zhou, "Adaptive Information Processing: An Effective Way to Improve Perceptron Branch Predictors", Journal of Instruction-Level Parallelism (JILP), Vol. 7, 2005.
• Hongliang Gao and Huiyang Zhou, "Adaptive Information Processing: An Effective Way to Improve Perceptron Branch Predictors", Champion, In the 1^st Championship Branch Prediction (CBP-1) held with the 37^th International Symposium on Microarchitecture (MICRO-37), Dec. 2004. (presentation, download the code, the simulation framework).